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Ú??RTr"c@?5!@??kR_!R*@?qT{*R=@5@a_q# @cQ@R?q'" RB Rc@Tr?0qITD Ě??Յh h`?ՄJj`T!Q@?jaT{R_RR_{S4@54@*qaTR @*@?,1`TSA@{è_@!4@"@A@R_R_@@`@@_A@{ST@a@95SA{¨_s_{ . @@a@aB9 @aJ9@aF9@`R @{¨_{S5T@`SA@{ƨ_`J@R!+ `RJ@!+`"RJ@!,` Rp@5o@1HT``@5J@R!``4qRR`R<qT_q(T!!(š6@ @B! !|@@ha?_{ @R6{R @@{_{ 3 @R6 @{¨_{@ @c! !|@?bh!_{ 3 @R (6 @*RR @{¨_@{ *ba_0qs` PzT? q`TB @Bh8aRR @{¨_`A{* @aRx2aR @ @RÌRÌnjprﾭﾭﾭﾭﾭ22@c6.2&: >CzPUY] 6.2&: >CzPUY]    pll_para_configpctl_startrk3399_spi_get_clksdram_initrk3399_spi_set_clklpddr4_set_ctlrk3399_gmac_set_clkread_mrlpddr4_set_raterk3399_dmc_initrk3399_dmc_of_to_platset_ds_odt;;<<:rk3399_sysconrockchip,rk3399-grfrockchip,rk3399-pmugrfrockchip,rk3399-pmusgrfrockchip,rk3399-cicrockchip,rk3399-pmuReturning to boot ROM... FATAL: unexpected command to back_to_bootrom() U-Boot TPL 2023.01 (Jan 03 2024 - 12:16:21) DRAM init failed: %d Trying to boot from %s TPL: failed to boot from all boot devices BOOTROMalloc space exhausted linux,phandle/aliases#address-cells#size-cellsstatusokayMissing DTB ### ERROR ### Please RESET the board ### #clock-cellsassigned-clock-parentsassigned-clocksassigned-clock-ratesclkclock-frequencyfixed_rate_raw_clockfixed_clockfixed-clockclock-divclock-multfixed_factor_clockfixed-factor-clockclock-output-namesclkin_gmacdo not support this i2c bus rockchip_sysreset%s: SPI clk-id %ld not supported %s: internal clock is UNIMPLEMENTED %s: the frequency can't be 0 Hz %s: Cannot find out a supported VCO for Frequency (%uHz). %s: Failed to match output frequency %u, difference is %u Hz,exceed 4MHZ Unsupported SDRAM frequency!,%ld rockchip_rk3399_pmucrurockchip,rk3399-pmucrurockchip_rk3399_crurockchip,rk3399-cruregcompatible/chosen/clocks/firmwarerootroot_drivernoprangessimple_bussimple-bussimple-mfdlittle-endianbig-endiannative-endianmiscrockchip_efuserockchip,rk3399-efuseramrockchip,sdram-params%s: Cannot read rockchip,sdram-params %d %s: regmap failed %d %s: pctl timeout! %s: read mr failed with 0x%x status %s: Unable to support LPDDR4 MR22 Soc ODT %s clk set failed %d %s: channel %d training failed! %s: change freq to %dMHz %d, %d 1: 0: %s clk get failed %d %s: Failed to init pctl channel 0 %s: Failed to init pctl channel 1 Channel 16bit error!!! full training error!!! Cap error! no ddrconfig find, Cap not support! %s: - %dMHz failed! %s DRAM init failed %d rockchip_rk3399_dmcrockchip,rk3399-dmcLPDDR2LPDDR3LPDDR4Unknown Device128B stride 512B stride 4K stride 32MB + 256B stride no stride , MHz Col= Bk= BG= CS0 Row=/ CS1 Row= CS= Die BW= Size=MB col error row errorreg-offsetreg-shiftreg-io-widthns16550_serialns16550ns16550aingenic,jz4780-uartnvidia,tegra20-uartsnps,dw-apb-uartOXNQSLXJGpnjsz   b%L   b%L  85  qj@'dP   1"    m `   d   4h(      7n @@ 0Pv    P(ddP    $c111MMMMMM $c111MMMMMM @ @ @2(       (V U UU31 32   @y PP vv   v0P@ vP ?#2+ h( 4 ( ZZUUZZUUZZUUZZUU      d ee    JK41MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM d     ."    l  vP @y2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @  @@**3 3 A ??UB @@**3 3UB @@**3 3jUB@UPd"     "@@DDDDDDDDd  r&L "$"!L/  85  qj@'dP   1"    m `   d   4h(      7n @@ 0Pv    P(ddP    $c111MMMMMM $c111MMMMMM @ @ @2(       (V U UU31 32   @y PP vv   v0P@ vP ?#2+ h( 4 ( ZZUUZZUUZZUUZZUU      d ee    JK41MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM d     ."    l  vP @y2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @  @@**3 3 A ??UB @@**3 3UB @@**3 3jUB@UPd"     "@@DDDDDDDDdrr)F#rr  @s7rr މ?r jŌ$F0ཌ(ŌnjпDP0ZǑʌZ${͌=Ō(E0HŒllfˌc(p (njB|sƌ0S GP`̌pnjnjdؾŒlPlfŌn͌7Č'ŌEnjBlf|njGnjZknjˌcܶnjdlŒloŌns *8(p(X(87pine64,rockpro64-v2.1pine64,rockpro64rockchip,rk3399 &Pine64 RockPro64 v2.1aliases,/serial@ff1800004/serial@ff1a0000Twm axiahbdclkokayvop@ff900000rockchip,rk3399-vop-bigP>Tvm axiahbdclkokaypinctrlrockchip,rk3399-pinctrl chosenserial2:1500000n8>same-as-spl/spi@ff1d0000/flash@0/mmc@fe320000/mmc@fe330000syscon@ff620000rockchip,rk3399-cicsysconPbdfi@ff630000Pc@rockchip,rk3399-dfimywdmcrockchip,rk3399-dmcTmP @ ( $"!"L $"!"L2  8 5 qj@'dP   "1   m `   d    H (     7n @@ P0v   Pd(dP   $c111MMMMMM $c111MMMMMM @  @@2(       (V UUU 133 2  y@P P v v    v0P@v P ?+2#  (H ( UUZZUUZZUUZZUUZZ      dee    KJ41MM$M1M1 MMM1$M1MM M1M1MM$M1M1 MMM1$M1MM M1M d     ".   l  vP y@vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ @ @ܺܺ**3 3 A ??U B@ @**3 3U B@ @**3 3jU B@UPd "      "@@DDDDDDDDdsyscon@ff330000rockchip,rk3399-pmusgrfsysconP3config> compatible#address-cells#size-cellsmodelserial0serial2mmc0mmc1mmc2spi1reginterruptsmax-frequencyclocksfifo-depthpower-domainsresetsreset-namesstatusbus-widthcap-sd-highspeedcd-gpiosdisable-wpvmmc-supplyvqmmc-supplyu-boot,spl-fifo-modearasan,soc-ctl-sysconclock-output-names#clock-cellsphysphy-namesdisable-cqe-dcmdmmc-hs200-1_8vnon-removablephandlereg-shiftreg-io-widthdmasdma-namesspi-max-frequencyrockchip,grf#reset-cells#phy-cellsiommusrockchip,pmurangesstdout-pathu-boot,spl-boot-orderdevfreq-eventsrockchip,sdram-paramsu-boot,spl-payload-offset  P@@TAB8? lTTT> @_ <!{@@D@B8 LT@TT8 t8x`X?Ak8D,@ 4T8D,@4T____6n@B@B:@C@d<C@A@b<@ @R_{S@? @?՟t-RNR}SRhRR R Q QQQ$$$$s$!$Bc qTg^ySR%S%*q4%BS'*4qc%QTy$$)DQ5EmS$qK! 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R ?`@@`4*@@g@?~4Z @@9R@R!?FlfK`@(Rt  2``@t2`_kDQBK<?`y?h`@@y<?Ks& T5?5?gR;RqTR6@[a@? @`4q`?տ *SA[BcCkDsE{Ǩ_R`Py<?ՠ$8|S8kӚ?Q ?ՠ?** &@?4C7T@8?!Q47H?Sb8Q"*5tK+&@? 6%IT 8LSS\R,`a[,````l))**"*2*E*V*h*y******** +.. y66666t\@.4 65:.&=Ui4Hl 5-5;5H5W5m5 |5511.|t-8A8U8i8Q}8Qd3x4`TP4o"8&C&X&m&s&y&&&&&&&&%& &&&&&&&'' 3 3ﾭﾭﾭﾭﾭ22@@ @ '@B@x}uu@x}e c`ppp@@@@@@@@@6.2&: >CzPUY] 6.2&: >CzPUY]      00@ a@@a`@a@a`a@a`a`ah fdt_fixup_memory_banksspl_perform_fixupsfit_find_config_nodepll_para_configsdhci_setup_cfgrk3399_emmc_get_physpl_load_fit_imagerk3399_spi_get_clksdhci_transfer_datark3399_emmc_phy_power_onspl_load_simple_fitfdt_record_loadablerk3399_spi_set_clksdhci_send_commandrockchip_sdhci_execute_tuningrk3399_gmac_set_clkrockchip_sdhci_probesdhci_resetfdt_find_or_add_subnodesdhci_initsdhci_set_clock(((((AAAAAABBBBBB #(-27FDT_ERR_NOTFOUNDFDT_ERR_EXISTSFDT_ERR_NOSPACEFDT_ERR_BADOFFSETFDT_ERR_BADPATHFDT_ERR_BADPHANDLEFDT_ERR_BADSTATEFDT_ERR_TRUNCATEDFDT_ERR_BADMAGICFDT_ERR_BADVERSIONFDT_ERR_BADSTRUCTUREFDT_ERR_BADLAYOUTFDT_ERR_INTERNALFDT_ERR_BADNCELLSFDT_ERR_BADVALUEFDT_ERR_BADOVERLAYFDT_ERR_NOPHANDLESFDT_ERR_BADFLAGS#address-cells#size-cellsstatusokayMissing DTB ### ERROR ### Please RESET the board ### %s:%dblk_partitionFATFAT32DOSEFI%s.%sidescsiusbsatahostnvmeefiloadervirtiopvblock#clock-cellsassigned-clock-parentsassigned-clocksassigned-clock-ratesclkclock-frequencyfixed_rate_raw_clockfixed_clockfixed-clockclock-divclock-multfixed_factor_clockfixed-factor-clockclock-output-namesclkin_gmacdo not support this i2c bus rockchip_sysreset%s: SPI clk-id %ld not supported %s: internal clock is UNIMPLEMENTED %s: the frequency can't be 0 Hz %s: Cannot find out a supported VCO for Frequency (%uHz). %s: Failed to match output frequency %u, difference is %u Hz,exceed 4MHZ Unsupported SDRAM frequency!,%ld rockchip_rk3399_pmucrurockchip,rk3399-pmucrurockchip_rk3399_crurockchip,rk3399-crucompatible/clocks/firmwarerootroot_drivernoprangessimple_bussimple-bussimple-mfdlittle-endianbig-endiannative-endian/configmiscrockchip_efuserockchip,rk3399-efuseno sysreset resetting ... MMC: block number 0x%lx exceeds max(0x%lx) mmc fail to send stop cmd Card did not respond to voltage select! : %d MMC: no card present unable to select a mode No ext_csd found! Select HS400 failed %d Select HS400ES failed %d unable to select a mode : %d cap-sd-highspeed%s %s: Invalid "bus-width" value %u! udevice *)(NULLcap-mmc-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104sd-uhs-ddr50mmc-ddr-1_8vmmc-ddr-1_2vmmc-hs200-1_8vmmc-hs200-1_2vmmc-hs400-1_8vmmc-hs400-1_2vmmc-hs400-enhanced-strobenon-removablecd-invertedbroken-cdno-1-8-vMMC Device %d not found mmc_blkfifo-depthu-boot,spl-fifo-modeclock-freq-min-maxrockchip_rk3288_dw_mshcrockchip,rk2928-dw-mshcrockchip,rk3288-dw-mshc%s: Reset 0x%x never completed. %s: MMC: %d busy timeout increasing to: %u ms. %s: Timeout for status update! %s: Transfer data timeout %s: Timeout to wait cmd & data inhibit %s: Error while setting tap delay %s: Internal clock never stabilised. %s: Aligned buffer alloc failed!!! sdhci-caps-masksdhci-caps%s: Hardware doesn't specify base clock frequency %s clk set rate fail! %s fail to get clk %s:Tuning failed %s: caldone timeout. phys%s Get syscon grf failedrockchip_sdhci_5_1arasan,sdhci-5.1rockchip,rk3568-dwcmshcspi_flashjedec_spi_norSF: Failed to set up slave jedec,spi-norspi-flashenabling reset hack; may not recover from unexpected reboots gpio-controllerpinconfigpinctrl-namespinctrl-%d%s %s: could not find pctldev rockchip,pinsrockchip,grfrockchip,pmubias-disablebias-bus-holdbias-pull-upbias-pull-downbias-pull-pin-defaultdrive-strengthinput-schmitt-disableinput-schmitt-enablerockchip_rk3399_pinctrlrockchip,rk3399-pinctrlgpio0gpio1gpio2gpio3gpio4rockchip_rk3399_dmcrockchip,rk3399-dmcstdout-pathconsoleNo serial driver foundreg-offsetreg-shiftreg-io-widthns16550_serialns16550ns16550aingenic,jz4780-uartnvidia,tegra20-uartsnps,dw-apb-uart%s %s: Cannot set speed (err=%d) %s %s: Cannot set mode (err=%d) spi-max-frequency%s %s: Invalid cs %d (err=%d) Invalid bus %d (err=%d) %s %s: Invalid chip select %d:%d (err=%d) spi-cpolspi-cphaspi-cs-highspi-3wirespi-half-duplexspi-tx-bus-widthspi-rx-bus-widthspi_generic_drvspi_genericspi-deactivate-delayspi-activate-delayrockchip_rk3288_spirockchip,rk3066-spirockchip,rk3288-spirockchip,rk3328-spirockchip,rk3368-spirockchip,rk3399-spijimnlheTwm axiahbdclkokayvop@ff900000rockchip,rk3399-vop-bigP>Tvm axiahbdclkokaypinctrlrockchip,rk3399-pinctrl chosenserial2:1500000n8>same-as-spl/spi@ff1d0000/flash@0/mmc@fe320000/mmc@fe330000syscon@ff620000rockchip,rk3399-cicsysconPbdfi@ff630000Pc@rockchip,rk3399-dfimywdmcrockchip,rk3399-dmcTmP @ ( $"!"L $"!"L2  8 5 qj@'dP   "1   m `   d    H (     7n @@ P0v   Pd(dP   $c111MMMMMM $c111MMMMMM @  @@2(       (V UUU 133 2  y@P P v v    v0P@v P ?+2#  (H ( UUZZUUZZUUZZUUZZ      dee    KJ41MM$M1M1 MMM1$M1MM M1M1MM$M1M1 MMM1$M1MM M1M d     ".   l  vP y@vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ @ @ܺܺ**3 3 A ??U B@ @**3 3U B@ @**3 3jU B@UPd "      "@@DDDDDDDDdsyscon@ff330000rockchip,rk3399-pmusgrfsysconP3config> compatible#address-cells#size-cellsmodelserial0serial2mmc0mmc1mmc2spi1reginterruptsmax-frequencyclocksfifo-depthpower-domainsresetsreset-namesstatusbus-widthcap-sd-highspeedcd-gpiosdisable-wpvmmc-supplyvqmmc-supplyu-boot,spl-fifo-modearasan,soc-ctl-sysconclock-output-names#clock-cellsphysphy-namesdisable-cqe-dcmdmmc-hs200-1_8vnon-removablephandlereg-shiftreg-io-widthdmasdma-namesspi-max-frequencyrockchip,grf#reset-cells#phy-cellsiommusrockchip,pmurangesstdout-pathu-boot,spl-boot-orderdevfreq-eventsrockchip,sdram-paramsu-boot,spl-payload-offset