8w(Tw`7phytec,am335x-wegaphytec,am335x-phycore-somti,am33xx&7Phytec AM335x phyBOARD-WEGAchosenaliases=/ocp/i2c@44e0b000B/ocp/i2c@4802a000G/ocp/i2c@4819c000L/ocp/serial@44e09000T/ocp/serial@48022000\/ocp/serial@48024000d/ocp/serial@481a6000l/ocp/serial@481a8000t/ocp/serial@481aa000|/ocp/can@481cc000/ocp/can@481d0000/ocp/usb@47400000/usb@47401000/ocp/usb@47400000/usb@47401800#/ocp/usb@47400000/usb-phy@47401300#/ocp/usb@47400000/usb-phy@47401b00&/ocp/ethernet@4a100000/slave@4a100200&/ocp/ethernet@4a100000/slave@4a100300/ocp/i2c@44e0b000/rtc@68/ocp/rtc@44e3e000memorymemoryȀcpuscpu@0arm,cortex-a8cpu  '( *28*cpupmuarm,cortex-a8-pmusocti,omap-inframpu ti,omap3-mpu'mpuocp simple-bus1'l3_mainl4_wkup@44c00000ti,am3-l4-wkupsimple-bus 1D(wkup_m3@100000ti,am3352-wkup-m3@  8umemdmem'wkup_m3Bam335x-pm-firmware.elfQ%W%prcm@200000 ti,am3-prcm @clocksclk_32768_ck_ fixed-clocklQWclk_rc32k_ck_ fixed-clockl}QWvirt_19200000_ck_ fixed-clockl$Q W virt_24000000_ck_ fixed-clockln6Q!W!virt_25000000_ck_ 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ti,mux-clockQWstm_clk_div_ck_ti,divider-clock|@trace_clk_div_ck_ti,divider-clock|@clkout2_ck_ti,gate-clockclockdomainsclk_24mhz_clkdmti,clockdomainscm@210000ti,am3-scmsimple-bus!  1! pinmux@800pinctrl-single8 pinmux_ethernet0@$ !! $ ( <!@!D Q;W;pinmux_mdio$H0LQ=W=pinmux_i2c0$((Q+W+pinmux_nandflashp$000 00000p0|Q?W?pinmux_spi0 $P T X0\0Q4W4pinmux_dcan1$hl2Q3W3pinmux_ethernet1p$@ D!H L P T X!\!`!d!h!l!t!x!Q<W<pinmux_mmc18$000000`7Q.W.pinmux_uart0$p0tQ)W)pinmux_uart1_pins $0x(|Q*W*scm_conf@0sysconQ1W1clockssys_clkin_ck_ ti,mux-clock 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disabledserial@481a8000ti,am3352-uartti,omap3-uart'uart5llH - disabledserial@481aa000ti,am3352-uartti,omap3-uart'uart6llH . disabledi2c@44e0b000 ti,omap4-i2c'i2c1DFokaydefault+lpmic@2d- ti,tps65910,,,,,, ,,regulatorsregulator@0$vrtc9regulator@1$vio9regulator@2$vdd1Mvdd_mpu\ tt9QWregulator@3$vdd2 Mvdd_core\ tt09regulator@4$vdd39regulator@5$vdig1 Mvdig1_1p8v\w@tw@regulator@6$vdig29regulator@7$vpll9regulator@8$vdac9regulator@9 $vaux19regulator@10 $vaux29regulator@11 $vaux339regulator@12 $vmmc\2Zt2Z9regulator@13 $vbbeeprom@52 atmel,24c32 Rokayrtc@68rv4162hokayi2c@4802a000 ti,omap4-i2c'i2c2HG disabledi2c@4819c000 ti,omap4-i2c'i2c3H disabledmmc@48060000ti,omap4-hsmmc'mmc1((txrx@&Hokay-default. /mmc@481d8000ti,omap4-hsmmc'mmc2((txrx&H disabledmmc@47810000ti,omap4-hsmmc'mmc3&G disabledspinlock@480ca000ti,omap4-hwspinlockH  'spinlockwdt@44e35000 ti,omap3-wdt 'wd_timer2DP[can@481cc000ti,am3352-d_can'd_can0H 0fck 1D4 disabledcan@481d0000ti,am3352-d_can'd_can1H 2fck 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simple-busfixedregulator@0regulator-fixedMvcc5v\LK@tLK@9Q,W,fixedregulator@1regulator-fixedMvcc3v3\2Zt2ZQ-W- #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3serial4serial5d_can0d_can1usb0usb1phy0phy1ethernet0ethernet1rtc0rtc1device_typeregoperating-pointsvoltage-toleranceclocksclock-namesclock-latencycpu0-supplyinterruptsti,hwmodsrangesreg-namesti,pm-firmwarelinux,phandle#clock-cellsclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-rate-parentti,bit-shiftti,index-power-of-twopinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsti,rprocmboxesinterrupt-controller#interrupt-cells#dma-cellsgpio-controller#gpio-cellsstatusdmasdma-namespinctrl-namespinctrl-0vcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-compatibleregulator-always-onregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onpagesizeti,dual-voltti,needs-special-resetti,needs-special-hs-handlingvmmc-supplybus-widthcd-gpios#hwlock-cellssyscon-raminit#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmti,spi-num-csspi-max-frequencym25p,fast-readlabelti,ctrl_modinterrupt-namesdr_modementor,multipointmentor,num-epsmentor,ram-bitsmentor,powerphys#dma-channels#dma-requests#pwm-cellscpdma_channelsale_entriesbd_ram_sizeno_bd_ramrx_descsmac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftsyscondual_emacbus_freqmac-addressphy_idphy-modedual_emac_res_vlanrmii-clock-ext#io-channel-cellsti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsnand-bus-widthti,nand-ecc-optgpmc,device-nandgpmc,device-widthgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wait-on-readgpmc,wait-on-writegpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-diffcsengpmc,clk-activation-nsgpmc,wait-monitoring-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nselm_id