v8 ( ` brcm,BCM963138DVTbrcm,bcm63138&Broadcom BCM963138DVT,chosen=console=ttyS0,115200F/ubus@fffe8000/serial@600aliasesR/ubus@fffe8000/serial@600X/ubus@fffe8000/serial@620memory^memoryjcpuscpu@0^cpuarm,cortex-a9njbrcm,bcm63138cpu@1^cpuarm,cortex-a9njbrcm,bcm63138 clocksarm_timer_clk fixed-clockeperiph_clk fixed-clockperiphaxi@80000000 simple-bus x@cache-controller@1d000arm,pl310-cachej  scu@1e000arm,cortex-a9-scujinterrupt-controller@1e100arm,cortex-a9-gicj$5timer@1e200arm,cortex-a9-global-timerj   Jlocal-timer@1e600arm,cortex-a9-twd-timerj   Jwatchdog@1e620arm,cortex-a9-twd-wdtj  reset-controller@4800c0brcm,bcm63138-pmbjHQreset-controller@4800e0brcm,bcm63138-pmbjHQubus@fffe8000 simple-bus timer@80brcm,bcm6328-timersysconj<serial@600brcm,bcm6345-uartj  J^periphjokayserial@620brcm,bcm6345-uartj  !J^periphjokaynand@20004brcm,nand-bcm63138brcm,brcmnand-v7.0brcm,brcmnandj qnandnand-int-basejokay &{nandnandcs@0 brcm,nandcsjbootlut@8000brcm,bcm63138-bootlutjPrebootsyscon-reboot4 #address-cells#size-cellscompatiblemodelinterrupt-parentbootargsstdout-pathuart0uart1device_typeregnext-level-cacheenable-methodresets#clock-cellsclock-frequencylinux,phandleclock-output-namesrangescache-unifiedcache-levelcache-sizecache-setscache-line-sizeinterrupts#interrupt-cellsinterrupt-controllerclocks#reset-cellsclock-namesstatusreg-namesinterrupt-namesnand-ecc-strengthnand-ecc-step-sizebrcm,nand-oob-sectors-sizeregmapoffsetmask