L8I(I#Hisilicon Hi4511 Development Board!hisilicon,hi3620-hi4511chosen,root=/dev/ram05serial0:115200n8aliasesA/amba/uart@b00000I/amba/uart@b01000Q/amba/uart@b02000Y/amba/uart@b03000a/amba/uart@b04000memoryimemoryu@ clk !fixed-clocky apb_pclkcpushisilicon,hi3620-smpcpu@0icpu!arm,cortex-a9ucpu@1!arm,cortex-a9icpuucpu@2!arm,cortex-a9icpuucpu@3!arm,cortex-a9icpuuamba !arm,amba-bus l2-cache!arm,pl310-cacheu  interrupt-controller@1000!arm,cortex-a9-gic$u system-controller@802000!hisilicon,sysctrl u 9DRclock@0!hisilicon,hi3620-clockuy dual_timer@800000!arm,sp804arm,primecellu` ! gapb_pclksokdual_timer@801000!arm,sp804arm,primecellu`"# gapb_pclk sdisableddual_timer@a01000!arm,sp804arm,primecellu`$% gapb_pclk sdisableddual_timer@a02000!arm,sp804arm,primecellu `&' gapb_pclk sdisableddual_timer@a03000!arm,sp804arm,primecellu0`a`() gapb_pclk sdisabledtimer@600!arm,cortex-a9-twd-timeru   uart@b00000!arm,pl011arm,primecellu ` gapb_pclksok zdefaultidleuart@b01000!arm,pl011arm,primecellu ` gapb_pclksok zdefaultidle  uart@b02000!arm,pl011arm,primecellu  ` gapb_pclksok zdefaultidle uart@b03000!arm,pl011arm,primecellu0 ` gapb_pclksok zdefaultidleuart@b04000!arm,pl011arm,primecellu@ ` gapb_pclksok zdefaultidlegpio@806000!arm,pl061arm,primecellu` @`$` gapb_pclkgpio@807000!arm,pl061arm,primecellup A$` gapb_pclkgpio@808000!arm,pl061arm,primecellu B  $` gapb_pclkgpio@809000!arm,pl061arm,primecellu C    $` gapb_pclkgpio@80a000!arm,pl061arm,primecellu D        $` gapb_pclkgpio@80b000!arm,pl061arm,primecellu E$` gapb_pclkgpio@80c000!arm,pl061arm,primecellu F$` gapb_pclkgpio@80d000!arm,pl061arm,primecellu G$` gapb_pclkgpio@80e000!arm,pl061arm,primecellu H !"$` gapb_pclkgpio@80f000!arm,pl061arm,primecellu Ip#$%&'()$` gapb_pclkgpio@810000!arm,pl061arm,primecellu J`+,--..$` gapb_pclkgpio@811000!arm,pl061arm,primecellu K/////011$` gapb_pclkgpio@812000!arm,pl061arm,primecellu  L12113334$` gapb_pclkgpio@813000!arm,pl061arm,primecellu0 M33555678$` gapb_pclkgpio@814000!arm,pl061arm,primecellu@ N9aa:;<<=$` gapb_pclkgpio@815000!arm,pl061arm,primecelluP O=>>??@@A$` gapb_pclkgpio@816000!arm,pl061arm,primecellu` PBCDEFGHI$` gapb_pclkgpio@817000!arm,pl061arm,primecellup QJKLMNOPQ$` gapb_pclk! !gpio@818000!arm,pl061arm,primecellu RRSSTTUVW$` gapb_pclkgpio@819000!arm,pl061arm,primecellu S@WWXX$` gapb_pclkgpio@81a000!arm,pl061arm,primecellu T`YYZZ[\$` gapb_pclkgpio@81b000!arm,pl061arm,primecellu U ^`$` gapb_pclkpinmux@803000!pinctrl-singleu0    +,1^`zdefault gpio-range+ board_pmx_pinsL uart0_pmx_funcL uart0_pmx_idleL uart1_pmx_funcL uart1_pmx_idleL  uart2_pmx_funcL  uart2_pmx_idleL uart3_pmx_funcL`d uart3_pmx_idleL`d uart4_pmx_funcLhlp uart4_pmx_idleLhlp i2c0_pmx_funcLi2c0_pmx_idleLi2c1_pmx_funcLi2c1_pmx_idleLi2c2_pmx_funcLhli2c2_pmx_idleLhli2c3_pmx_funcLPTi2c3_pmx_idleLPTspi0_pmx_func(Lspi0_pmx_idle(Lspi1_pmx_funcLspi1_pmx_idleLkpc_pmx_func0L,04 kpc_pmx_idle0L,04 gpio_key_funcL 0emmc_pmx_func(L0$(,emmc_pmx_idle(L0$(,sd_pmx_funcLsd_pmx_idleLnand_pmx_funcHL  $(,nand_pmx_idleHL  $(,sdio_pmx_funcLsdio_pmx_idleLaudio_out_pmx_funcLpinmux@803800!pinconf-singleu8 zdefault board_pu_pins L `} board_pd_pinsL8PT`} board_pd_ps_pinsL`}0 board_np_pinsLL`} board_ps_pinsL0 uart0_cfg_funcL `} uart0_cfg_idleL `} uart1_cfg_func L`}  uart1_cfg_idle L`}  uart2_cfg_func L $(,`}  uart2_cfg_idle L $(,`} uart3_cfg_func L`} uart3_cfg_idle L`} uart4_cfg_func L`} i2c0_cfg_funcL|`}0i2c1_cfg_funcL`}0i2c2_cfg_funcL`}0i2c3_cfg_funcL`}0spi0_cfg_func1L`}0spi0_cfg_func2 L`}0spi1_cfg_func1L`}0spi1_cfg_func2L`}0kpc_cfg_func0LPTX048`} emmc_cfg_funchLXdh`}0sd_cfg_func1L`}0sd_cfg_func2 L`}pnand_cfg_func1L<@lptx|`}0nand_cfg_func2PLDHLPTX\`dh`}0sdio_cfg_func0L`}0audio_out_cfg_funcL`}  gpio-keys !gpio-keyscallcall ! #address-cells#size-cellsmodelcompatiblebootargsstdout-pathserial0serial1serial2serial3serial4device_typereg#clock-cellsclock-frequencyclock-output-namesenable-methodnext-level-cacheinterrupt-parentrangesinterruptscache-unifiedcache-levellinux,phandle#interrupt-cellsinterrupt-controllersmp-offsetresume-offsetreboot-offsetclocksclock-namesstatuspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cellsgpio-ranges#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthlabelgpioslinux,code