H(8 ",Hisilicon HIP01 Development Board&2hisilicon,hip01-ca9x2hisilicon,hip01chosenaliasesmemory=memoryIinterrupt-controller@1e0010002arm,cortex-a9-gicM^Isyrefclk144mkhz 2fixed-clockDhisi:refclk144khzsysoc 2simple-bus  amba 2arm,amba-busuart@100010002snps,dw-apb-uartI apb_pclk okayuart@100020002snps,dw-apb-uartI  apb_pclk ! disableduart@100030002snps,dw-apb-uartI0 apb_pclk " disableduart@100060002snps,dw-apb-uartI` apb_pclk  disabledsystem-controller@10000000*2hisilicon,hip01-sysctrlhisilicon,sysctrlIglobal_timer@0a0002002arm,cortex-a9-global-timerI   local_timer@0a0006002arm,cortex-a9-twd-timerI   cpushisilicon,hip01-smpcpu@0=cpu2arm,cortex-a9Icpu@1=cpu2arm,cortex-a9I #address-cells#size-cellsinterrupt-parentmodelcompatibledevice_typereg#interrupt-cellsinterrupt-controllerlinux,phandle#clock-cellsclock-frequencyclock-output-namesrangesclocksclock-namesreg-shiftinterruptsstatusreboot-offsetenable-method