Ð þí:Ã89¼(9„ Hisilicon D01 Development Board!hisilicon,hip04-d01aliases,/soc/uart@4007000bootwrapper!hisilicon,hip04-bootwrapper4Ààcpuscpu-mapcluster0core0@core1@core2@core3@cluster1core0@core1@core2@core3@cluster2core0@ core1@ core2@ core3@ cluster3core0@ core1@core2@core3@cpu@0Dcpu!arm,cortex-a15PTZcpu@1Dcpu!arm,cortex-a15PTZcpu@2Dcpu!arm,cortex-a15PTZcpu@3Dcpu!arm,cortex-a15PTZcpu@100Dcpu!arm,cortex-a15PTZcpu@101Dcpu!arm,cortex-a15PTZcpu@102Dcpu!arm,cortex-a15PTZcpu@103Dcpu!arm,cortex-a15PTZcpu@200Dcpu!arm,cortex-a15PT Z cpu@201Dcpu!arm,cortex-a15PT Z cpu@202Dcpu!arm,cortex-a15PT Z cpu@203Dcpu!arm,cortex-a15PT Z cpu@300Dcpu!arm,cortex-a15PT Z cpu@301Dcpu!arm,cortex-a15PTZcpu@302Dcpu!arm,cortex-a15PTZcpu@303Dcpu!arm,cortex-a15PTZtimer!arm,armv7-timerb0s   clk_50m~ !fixed-clock‹úð€TZclk_168m~ !fixed-clock‹ zTZclk_375m~ !fixed-clock‹Z ÀTZsoc !simple-busb›àinterrupt-controller@c01000!hisilicon,hip04-intc¢³ s  PÀÀ À@ À` TZsysctrl!hisilicon,sysctrlPàfabric!hisilicon,hip04-fabricP dual_timer@3000000!arm,sp804arm,primecellP sàÈ Ïapb_pclkarm-pmu!arm,cortex-a15-pmuÀs@ABCDEFGHIJKLMNOuart@4007000!snps,dw-apb-uartPp s}ÈÏuartclkÛåoksata@a000000!hisilicon,hisi-ahciP  stetb@0,e3c42000"!arm,coresight-etb10arm,primecellPãÄ È Ïapb_pclkportendpoint@0ì÷TZetb@0,e3c82000"!arm,coresight-etb10arm,primecellPãÈ È Ïapb_pclkportendpoint@0ì÷TZetb@0,e3cc2000"!arm,coresight-etb10arm,primecellPãÌ È Ïapb_pclkportendpoint@0ì÷T Z etb@0,e3d02000"!arm,coresight-etb10arm,primecellPãÐ È Ïapb_pclkportendpoint@0ì÷T#Z#tpiu@0,e3c05000!!arm,coresight-tpiuarm,primecellPãÀPÈ Ïapb_pclkportendpoint@0ì÷T:Z:replicator0!arm,coresight-replicatorportsport@0Pendpoint÷TZport@1Pendpoint÷T;Z;port@2Pendpointì÷T&Z&replicator1!arm,coresight-replicatorportsport@0Pendpoint÷TZport@1Pendpoint÷T<Z<port@2Pendpointì÷T+Z+replicator2!arm,coresight-replicatorportsport@0Pendpoint÷ TZport@1Pendpoint÷!T=Z=port@2Pendpointì÷"T0Z0replicator3!arm,coresight-replicatorportsport@0Pendpoint÷#TZport@1Pendpoint÷$T>Z>port@2Pendpointì÷%T5Z5funnel@0,e3c41000#!arm,coresight-funnelarm,primecellPãÄÈ Ïapb_pclkportsport@0Pendpoint÷&TZport@1Pendpointì÷'T?Z?port@2Pendpointì÷(T@Z@port@3Pendpointì÷)TAZAport@4Pendpointì÷*TBZBfunnel@0,e3c81000#!arm,coresight-funnelarm,primecellPãÈÈ Ïapb_pclkportsport@0Pendpoint÷+TZport@1Pendpointì÷,TCZCport@2Pendpointì÷-TDZDport@3Pendpointì÷.TEZEport@4Pendpointì÷/TFZFfunnel@0,e3cc1000#!arm,coresight-funnelarm,primecellPãÌÈ Ïapb_pclkportsport@0Pendpoint÷0T"Z"port@1Pendpointì÷1TGZGport@2Pendpointì÷2THZHport@3Pendpointì÷3TIZIport@4Pendpointì÷4TJZJfunnel@0,e3d01000#!arm,coresight-funnelarm,primecellPãÐÈ Ïapb_pclkportsport@0Pendpoint÷5T%Z%port@1Pendpointì÷6TKZKport@2Pendpointì÷7TLZLport@3Pendpointì÷8TMZMport@4Pendpointì÷9TNZNfunnel@0,e3c04000#!arm,coresight-funnelarm,primecellPãÀ@È Ïapb_pclkportsport@0Pendpoint÷:TZport@1Pendpointì÷;TZport@2Pendpointì÷<TZport@3Pendpointì÷=T!Z!port@4Pendpointì÷>T$Z$ptm@0,e3c7c000"!arm,coresight-etm3xarm,primecellPãÇÀÈ Ïapb_pclk@portendpoint÷?T'Z'ptm@0,e3c7d000"!arm,coresight-etm3xarm,primecellPãÇÐÈ Ïapb_pclk@portendpoint÷@T(Z(ptm@0,e3c7e000"!arm,coresight-etm3xarm,primecellPãÇàÈ Ïapb_pclk@portendpoint÷AT)Z)ptm@0,e3c7f000"!arm,coresight-etm3xarm,primecellPãÇðÈ Ïapb_pclk@portendpoint÷BT*Z*ptm@0,e3cbc000"!arm,coresight-etm3xarm,primecellPãËÀÈ Ïapb_pclk@portendpoint÷CT,Z,ptm@0,e3cbd000"!arm,coresight-etm3xarm,primecellPãËÐÈ Ïapb_pclk@portendpoint÷DT-Z-ptm@0,e3cbe000"!arm,coresight-etm3xarm,primecellPãËàÈ Ïapb_pclk@portendpoint÷ET.Z.ptm@0,e3cbf000"!arm,coresight-etm3xarm,primecellPãËðÈ Ïapb_pclk@portendpoint÷FT/Z/ptm@0,e3cfc000"!arm,coresight-etm3xarm,primecellPãÏÀÈ Ïapb_pclk@ portendpoint÷GT1Z1ptm@0,e3cfd000"!arm,coresight-etm3xarm,primecellPãÏÐÈ Ïapb_pclk@ portendpoint÷HT2Z2ptm@0,e3cfe000"!arm,coresight-etm3xarm,primecellPãÏàÈ Ïapb_pclk@ portendpoint÷IT3Z3ptm@0,e3cff000"!arm,coresight-etm3xarm,primecellPãÏðÈ Ïapb_pclk@ portendpoint÷JT4Z4ptm@0,e3d3c000"!arm,coresight-etm3xarm,primecellPãÓÀÈ Ïapb_pclk@ portendpoint÷KT6Z6ptm@0,e3d3d000"!arm,coresight-etm3xarm,primecellPãÓÐÈ Ïapb_pclk@portendpoint÷LT7Z7ptm@0,e3d3e000"!arm,coresight-etm3xarm,primecellPãÓàÈ Ïapb_pclk@portendpoint÷MT8Z8ptm@0,e3d3f000"!arm,coresight-etm3xarm,primecellPãÓðÈ Ïapb_pclk@portendpoint÷NT9Z9memory@00000000,10000000Dmemory PÀÀ@ #address-cells#size-cellsmodelcompatibleserial0boot-methodcpudevice_typereglinux,phandleinterrupt-parentinterrupts#clock-cellsclock-frequencyranges#interrupt-cellsinterrupt-controllerclocksclock-namesreg-shiftstatusslave-moderemote-endpoint