)8(('$Hisilicon HIX5HD2 Development Board!hisilicon,hix5hd2chosen,serial0:115200n8aliases8/soc/amba/uart@00b00000memory@memoryLinterrupt-controller@f8a01000!arm,cortex-a9-gicPaLv|soc !simple-bus amba !arm,amba-bustimer@00002000!arm,sp804arm,primecellL  okaytimer@00a29000!arm,sp804arm,primecellL  disabledtimer@00a2a000!arm,sp804arm,primecellL  disabledtimer@00a2b000!arm,sp804arm,primecellL  disabledtimer@00a81000!arm,sp804arm,primecellL  disableduart@00b00000!arm,pl011arm,primecellL 1 apb_pclkokayuart@00006000!arm,pl011arm,primecellL` 2 apb_pclk disableduart@00b02000!arm,pl011arm,primecellL  3 apb_pclk disableduart@00b03000!arm,pl011arm,primecellL0 4 apb_pclk disableduart@00b04000!arm,pl011arm,primecellL@ 5 apb_pclk disabledgpio@b20000!arm,pl061arm,primecellL l  apb_pclkaP disabledgpio@b21000!arm,pl061arm,primecellL m  apb_pclkaP disabledgpio@b22000!arm,pl061arm,primecellL  n  apb_pclkaP disabledgpio@b23000!arm,pl061arm,primecellL0 o  apb_pclkaP disabledgpio@b24000!arm,pl061arm,primecellL@ p  apb_pclkaP disabledgpio@004000!arm,pl061arm,primecellL@ q  apb_pclkaP disabledgpio@b26000!arm,pl061arm,primecellL` r  apb_pclkaP disabledgpio@b27000!arm,pl061arm,primecellLp s  apb_pclkaP disabledgpio@b28000!arm,pl061arm,primecellL t  apb_pclkaP disabledgpio@b29000!arm,pl061arm,primecellL u  apb_pclkaP disabledgpio@b2a000!arm,pl061arm,primecellL v  apb_pclkaP disabledgpio@b2b000!arm,pl061arm,primecellL w  apb_pclkaP disabledgpio@b2c000!arm,pl061arm,primecellL x  apb_pclkaP disabledgpio@b2d000!arm,pl061arm,primecellL y  apb_pclkaP disabledgpio@b2e000!arm,pl061arm,primecellL z  apb_pclkaP disabledgpio@b2f000!arm,pl061arm,primecellL {  apb_pclkaP disabledgpio@b30000!arm,pl061arm,primecellL |  apb_pclkaP disabledgpio@b31000!arm,pl061arm,primecellL }  apb_pclkaP disabledwatchdog@a2c000!arm,sp805arm,primecellL  apb_pclklocal_timer@00a00600!arm,cortex-a9-twd-timerL   l2-cache!arm,pl310-cacheL v|system-controller@00000000!hisilicon,sysctrlsysconLv|reboot!syscon-rebootޭcpuctrl@00a22000!hisilicon,cpuctrlL  clock@0!hisilicon,hix5hd2-clockL !v|mmc@1830000 !snps,dw-mshcL #ciubiummc@1820000 !snps,dw-mshcL "ciubiuethernet@1840000!hisilicon,hix5hd2-gmacL0  Gokay.9miiBethernet-phy@2Lv|ethernet@1841000!hisilicon,hix5hd2-gmacL0 Hokay.9rgmiiBethernet-phy@1Lv|ehci@1890000 !generic-ehciL Bohci@1880000 !generic-ohciL Csyscon@a20000!sysconLv|phy@1900000!hisilicon,hix5hd2-sata-phyLNYu v|sata@1900000!hisilicon,hisi-ahciL F sata-phyir@001000!hisilicon,hix5hd2-irL /i2c@b10000!hisilicon,hix5hd2-i2cL & disabledi2c@b11000!hisilicon,hix5hd2-i2cL ' disabledi2c@b12000!hisilicon,hix5hd2-i2cL  ( disabledi2c@b13000!hisilicon,hix5hd2-i2cL0 ) disabledi2c@b16000!hisilicon,hix5hd2-i2cL` + disabledi2c@b17000!hisilicon,hix5hd2-i2cLp , disabledcpushisilicon,hix5hd2-smpcpu@0!arm,cortex-a9@cpuLcpu@1!arm,cortex-a9@cpuL #address-cells#size-cellsmodelcompatiblestdout-pathserial0device_typereg#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterruptsclocksstatusclock-namesgpio-controller#gpio-cellsarm,primecell-periphidcache-unifiedcache-levelregmapoffsetmask#clock-cellsphy-handlephy-modemac-address#phy-cellshisilicon,peripheral-sysconhisilicon,power-regphysphy-nameshisilicon,power-sysconenable-methodnext-level-cache