8(3logicpd,dm3730-torpedo-devkitti,omap3630ti,omap3&,7LogicPD Zoom DM3730 Torpedo Development Kitchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000memorylmemoryxcpuscpu@0arm,cortex-a8lcpux|cpus 'O 57pmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busxh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busx  pinmux@30 ti,omap3-padconfpinctrl-singlex087=pinmux_mm3_pins0E468:T^7=pinmux_twl4030_pinsEA7=pinmux_gpio_key_pinsE7=pinmux_led_pinsE7=pinmux_mmc1_pins0E7=scm_conf@270sysconsimple-busxp0 p07=pbias_regulatorti,pbias-omap3ti,pbias-omapxYpbias_mmc_omap2430`pbias_mmc_omap2430ow@-7=clocksmcbsp5_mux_fckti,composite-mux-clock|xh7=mcbsp5_fckti,composite-clock|mcbsp1_mux_fckti,composite-mux-clock|x7 = mcbsp1_fckti,composite-clock| mcbsp2_mux_fckti,composite-mux-clock| x7 = mcbsp2_fckti,composite-clock| mcbsp3_mux_fckti,composite-mux-clock| xh7=mcbsp3_fckti,composite-clock|mcbsp4_mux_fckti,composite-mux-clock| xh7=mcbsp4_fckti,composite-clock|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \pinmux_twl4030_vpins E7=pinmux_gpio_key_pins_wkupE 7=pinmux_lan9221_pinsEZ7=pinmux_mmc1_cdET7=aes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocksvirt_16_8m_ck fixed-clockY7=osc_sys_ck ti,mux-clock|x @7=sys_ckti,divider-clock|xp7=sys_clkout1ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|7=dpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock|7=wkup_l4_ickfixed-factor-clock|7N=Ncorex2_d3_fckfixed-factor-clock|7=corex2_d5_fckfixed-factor-clock|7=clockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock7@=@virt_12m_ck fixed-clock7=virt_13m_ck fixed-clock]@7=virt_19200000_ck fixed-clock$7=virt_26000000_ck fixed-clock7=virt_38_4m_ck fixed-clockI7=dpll4_ckti,omap3-dpll-per-j-type-clock|x D 07=dpll4_m2_ckti,divider-clock|?x H7 = dpll4_m2x2_mul_ckfixed-factor-clock| 7!=!dpll4_m2x2_ckti,hsdiv-gate-clock|!x 7"="omap_96m_alwon_fckfixed-factor-clock|"7)=)dpll3_ckti,omap3-dpll-core-clock|x @ 07=dpll3_m3_ckti,divider-clock|x@7#=#dpll3_m3x2_mul_ckfixed-factor-clock|#7$=$dpll3_m3x2_ckti,hsdiv-gate-clock|$ x 7%=%emu_core_alwon_ckfixed-factor-clock|%7b=bsys_altclk fixed-clock7.=.mcbsp_clks fixed-clock7=dpll3_m2_ckti,divider-clock|x @7=core_ckfixed-factor-clock|7&=&dpll1_fckti,divider-clock|&x @7'='dpll1_ckti,omap3-dpll-clock|'x  $ @ 47=dpll1_x2_ckfixed-factor-clock|7(=(dpll1_x2m2_ckti,divider-clock|(x D7<=<cm_96m_fckfixed-factor-clock|)7*=*omap_96m_fck ti,mux-clock|*x @7E=Edpll4_m3_ckti,divider-clock| x@7+=+dpll4_m3x2_mul_ckfixed-factor-clock|+7,=,dpll4_m3x2_ckti,hsdiv-gate-clock|,x 7-=-omap_54m_fck ti,mux-clock|-.x @78=8cm_96m_d2_fckfixed-factor-clock|*7/=/omap_48m_fck ti,mux-clock|/.x @70=0omap_12m_fckfixed-factor-clock|07G=Gdpll4_m4_ckti,divider-clock| x@71=1dpll4_m4x2_mul_ckti,fixed-factor-clock|1%3@72=2dpll4_m4x2_ckti,gate-clock|2x @7=dpll4_m5_ckti,divider-clock|?x@73=3dpll4_m5x2_mul_ckti,fixed-factor-clock|3%3@74=4dpll4_m5x2_ckti,hsdiv-gate-clock|4x @7j=jdpll4_m6_ckti,divider-clock|?x@75=5dpll4_m6x2_mul_ckfixed-factor-clock|576=6dpll4_m6x2_ckti,hsdiv-gate-clock|6x 77=7emu_per_alwon_ckfixed-factor-clock|77c=cclkout2_src_gate_ck ti,composite-no-wait-gate-clock|&x p79=9clkout2_src_mux_ckti,composite-mux-clock|&*8x p7:=:clkout2_src_ckti,composite-clock|9:7;=;sys_clkout2ti,divider-clock|;@x pSmpu_ckfixed-factor-clock|<7===arm_fckti,divider-clock|=x $emu_mpu_alwon_ckfixed-factor-clock|=7d=dl3_ickti,divider-clock|&x @7>=>l4_ickti,divider-clock|>x @7?=?rm_ickti,divider-clock|?x @gpt10_gate_fckti,composite-gate-clock| x 7A=Agpt10_mux_fckti,composite-mux-clock|@x @7B=Bgpt10_fckti,composite-clock|ABgpt11_gate_fckti,composite-gate-clock| x 7C=Cgpt11_mux_fckti,composite-mux-clock|@x @7D=Dgpt11_fckti,composite-clock|CDcore_96m_fckfixed-factor-clock|E7=mmchs2_fckti,wait-gate-clock|x 7=mmchs1_fckti,wait-gate-clock|x 7=i2c3_fckti,wait-gate-clock|x 7=i2c2_fckti,wait-gate-clock|x 7=i2c1_fckti,wait-gate-clock|x 7=mcbsp5_gate_fckti,composite-gate-clock| x 7=mcbsp1_gate_fckti,composite-gate-clock| x 7 = core_48m_fckfixed-factor-clock|07F=Fmcspi4_fckti,wait-gate-clock|Fx 7=mcspi3_fckti,wait-gate-clock|Fx 7=mcspi2_fckti,wait-gate-clock|Fx 7=mcspi1_fckti,wait-gate-clock|Fx 7=uart2_fckti,wait-gate-clock|Fx 7=uart1_fckti,wait-gate-clock|Fx  7=core_12m_fckfixed-factor-clock|G7H=Hhdq_fckti,wait-gate-clock|Hx 7=core_l3_ickfixed-factor-clock|>7I=Isdrc_ickti,wait-gate-clock|Ix 7=gpmc_fckfixed-factor-clock|Icore_l4_ickfixed-factor-clock|?7J=Jmmchs2_ickti,omap3-interface-clock|Jx 7=mmchs1_ickti,omap3-interface-clock|Jx 7=hdq_ickti,omap3-interface-clock|Jx 7=mcspi4_ickti,omap3-interface-clock|Jx 7=mcspi3_ickti,omap3-interface-clock|Jx 7=mcspi2_ickti,omap3-interface-clock|Jx 7=mcspi1_ickti,omap3-interface-clock|Jx 7=i2c3_ickti,omap3-interface-clock|Jx 7=i2c2_ickti,omap3-interface-clock|Jx 7=i2c1_ickti,omap3-interface-clock|Jx 7=uart2_ickti,omap3-interface-clock|Jx 7=uart1_ickti,omap3-interface-clock|Jx  7=gpt11_ickti,omap3-interface-clock|Jx  7=gpt10_ickti,omap3-interface-clock|Jx  7=mcbsp5_ickti,omap3-interface-clock|Jx  7=mcbsp1_ickti,omap3-interface-clock|Jx  7=omapctrl_ickti,omap3-interface-clock|Jx 7=dss_tv_fckti,gate-clock|8x7=dss_96m_fckti,gate-clock|Ex7=dss2_alwon_fckti,gate-clock|x7=dummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock|x 7K=Kgpt1_mux_fckti,composite-mux-clock|@x @7L=Lgpt1_fckti,composite-clock|KLaes2_ickti,omap3-interface-clock|Jx 7=wkup_32k_fckfixed-factor-clock|@7M=Mgpio1_dbckti,gate-clock|Mx 7=sha12_ickti,omap3-interface-clock|Jx 7=wdt2_fckti,wait-gate-clock|Mx 7=wdt2_ickti,omap3-interface-clock|Nx 7=wdt1_ickti,omap3-interface-clock|Nx 7=gpio1_ickti,omap3-interface-clock|Nx 7=omap_32ksync_ickti,omap3-interface-clock|Nx 7=gpt12_ickti,omap3-interface-clock|Nx 7=gpt1_ickti,omap3-interface-clock|Nx 7=per_96m_fckfixed-factor-clock|)7 = per_48m_fckfixed-factor-clock|07O=Ouart3_fckti,wait-gate-clock|Ox 7=gpt2_gate_fckti,composite-gate-clock|x7P=Pgpt2_mux_fckti,composite-mux-clock|@x@7Q=Qgpt2_fckti,composite-clock|PQgpt3_gate_fckti,composite-gate-clock|x7R=Rgpt3_mux_fckti,composite-mux-clock|@x@7S=Sgpt3_fckti,composite-clock|RSgpt4_gate_fckti,composite-gate-clock|x7T=Tgpt4_mux_fckti,composite-mux-clock|@x@7U=Ugpt4_fckti,composite-clock|TUgpt5_gate_fckti,composite-gate-clock|x7V=Vgpt5_mux_fckti,composite-mux-clock|@x@7W=Wgpt5_fckti,composite-clock|VWgpt6_gate_fckti,composite-gate-clock|x7X=Xgpt6_mux_fckti,composite-mux-clock|@x@7Y=Ygpt6_fckti,composite-clock|XYgpt7_gate_fckti,composite-gate-clock|x7Z=Zgpt7_mux_fckti,composite-mux-clock|@x@7[=[gpt7_fckti,composite-clock|Z[gpt8_gate_fckti,composite-gate-clock| x7\=\gpt8_mux_fckti,composite-mux-clock|@x@7]=]gpt8_fckti,composite-clock|\]gpt9_gate_fckti,composite-gate-clock| x7^=^gpt9_mux_fckti,composite-mux-clock|@x@7_=_gpt9_fckti,composite-clock|^_per_32k_alwon_fckfixed-factor-clock|@7`=`gpio6_dbckti,gate-clock|`x7=gpio5_dbckti,gate-clock|`x7=gpio4_dbckti,gate-clock|`x7=gpio3_dbckti,gate-clock|`x7=gpio2_dbckti,gate-clock|`x 7=wdt3_fckti,wait-gate-clock|`x 7=per_l4_ickfixed-factor-clock|?7a=agpio6_ickti,omap3-interface-clock|ax7=gpio5_ickti,omap3-interface-clock|ax7=gpio4_ickti,omap3-interface-clock|ax7=gpio3_ickti,omap3-interface-clock|ax7=gpio2_ickti,omap3-interface-clock|ax 7=wdt3_ickti,omap3-interface-clock|ax 7=uart3_ickti,omap3-interface-clock|ax 7=uart4_ickti,omap3-interface-clock|ax7=gpt9_ickti,omap3-interface-clock|ax 7=gpt8_ickti,omap3-interface-clock|ax 7=gpt7_ickti,omap3-interface-clock|ax7=gpt6_ickti,omap3-interface-clock|ax7=gpt5_ickti,omap3-interface-clock|ax7=gpt4_ickti,omap3-interface-clock|ax7=gpt3_ickti,omap3-interface-clock|ax7=gpt2_ickti,omap3-interface-clock|ax7=mcbsp2_ickti,omap3-interface-clock|ax7=mcbsp3_ickti,omap3-interface-clock|ax7=mcbsp4_ickti,omap3-interface-clock|ax7=mcbsp2_gate_fckti,composite-gate-clock|x7 = mcbsp3_gate_fckti,composite-gate-clock|x7=mcbsp4_gate_fckti,composite-gate-clock|x7=emu_src_mux_ck ti,mux-clock|bcdx@7e=eemu_src_ckti,clkdm-gate-clock|e7f=fpclk_fckti,divider-clock|fx@pclkx2_fckti,divider-clock|fx@atclk_fckti,divider-clock|fx@traceclk_src_fck ti,mux-clock|bcdx@7g=gtraceclk_fckti,divider-clock|g x@secure_32k_fck fixed-clock7h=hgpt12_fckfixed-factor-clock|hwdt1_fckfixed-factor-clock|hsecurity_l4_ick2fixed-factor-clock|?7i=iaes1_ickti,omap3-interface-clock|ix rng_ickti,omap3-interface-clock|ix sha11_ickti,omap3-interface-clock|ix des1_ickti,omap3-interface-clock|ix cam_mclkti,gate-clock|jx@cam_ick!ti,omap3-no-wait-interface-clock|?x7=csi2_96m_fckti,gate-clock|x7=security_l3_ickfixed-factor-clock|>7k=kpka_ickti,omap3-interface-clock|kx icr_ickti,omap3-interface-clock|Jx des2_ickti,omap3-interface-clock|Jx mspro_ickti,omap3-interface-clock|Jx mailboxes_ickti,omap3-interface-clock|Jx ssi_l4_ickfixed-factor-clock|?7r=rsr1_fckti,wait-gate-clock|x sr2_fckti,wait-gate-clock|x sr_l4_ickfixed-factor-clock|?dpll2_fckti,divider-clock|&x@7l=ldpll2_ckti,omap3-dpll-clock|lx$@4i{7m=mdpll2_m2_ckti,divider-clock|mxD7n=niva2_ckti,wait-gate-clock|nx7=modem_fckti,omap3-interface-clock|x 7=sad2d_ickti,omap3-interface-clock|>x 7=mad2d_ickti,omap3-interface-clock|>x 7=mspro_fckti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock|x 7o=ossi_ssr_div_fck_3430es2ti,composite-divider-clock|x @$7p=pssi_ssr_fck_3430es2ti,composite-clock|op7q=qssi_sst_fck_3430es2fixed-factor-clock|q7=hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock|Ix 7=ssi_ick_3430es2ti,omap3-ssi-interface-clock|rx 7=usim_gate_fckti,composite-gate-clock|E x 7}=}sys_d2_ckfixed-factor-clock|7t=tomap_96m_d2_fckfixed-factor-clock|E7u=uomap_96m_d4_fckfixed-factor-clock|E7v=vomap_96m_d8_fckfixed-factor-clock|E7w=womap_96m_d10_fckfixed-factor-clock|E 7x=xdpll5_m2_d4_ckfixed-factor-clock|s7y=ydpll5_m2_d8_ckfixed-factor-clock|s7z=zdpll5_m2_d16_ckfixed-factor-clock|s7{={dpll5_m2_d20_ckfixed-factor-clock|s7|=|usim_mux_fckti,composite-mux-clock(|tuvwxyz{|x @7~=~usim_fckti,composite-clock|}~usim_ickti,omap3-interface-clock|Nx  7=dpll5_ckti,omap3-dpll-clock|x  $ L 4i{7=dpll5_m2_ckti,divider-clock|x P7s=ssgx_gate_fckti,composite-gate-clock|&x 7=core_d3_ckfixed-factor-clock|&7=core_d4_ckfixed-factor-clock|&7=core_d6_ckfixed-factor-clock|&7=omap_192m_alwon_fckfixed-factor-clock|"7=core_d2_ckfixed-factor-clock|&7=sgx_mux_fckti,composite-mux-clock |*x @7=sgx_fckti,composite-clock|sgx_ickti,wait-gate-clock|>x 7=cpefuse_fckti,gate-clock|x 7=ts_fckti,gate-clock|@x 7=usbtll_fckti,wait-gate-clock|sx 7=usbtll_ickti,omap3-interface-clock|Jx 7=mmchs3_ickti,omap3-interface-clock|Jx 7=mmchs3_fckti,wait-gate-clock|x 7=dss1_alwon_fck_3430es2ti,dss-gate-clock|x@7=dss_ick_3430es2ti,omap3-dss-interface-clock|?x7=usbhost_120m_fckti,gate-clock|sx7=usbhost_48m_fckti,dss-gate-clock|0x7=usbhost_ickti,omap3-dss-interface-clock|?x7=uart4_fckti,wait-gate-clock|Ox7=clockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|fdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|md2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH 7=dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `7=gpio@48310000ti,omap3-gpioxH1gpio17=gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio47=gpio@49056000ti,omap3-gpioxI`!gpio57=gpio@49058000ti,omap3-gpioxI"gpio67=serial@4806a000ti,omap3-uartxH HR12txrxuart1lserial@4806c000ti,omap3-uartxHI34txrxuart2lserial@49020000ti,omap3-uartxIJ56txrxuart3li2c@48070000 ti,omap3-i2cxH8txrxi2c1'@twl@48xH& ti,twl4030 defaultrtcti,twl4030-rtc bciti,twl4030-bci "00<watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1o ' 7=regulator-vdacti,twl4030-vdacow@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1o:07=regulator-vmmc2ti,twl4030-vmmc2o:07=regulator-vusb1v5ti,twl4030-vusb1v57=regulator-vusb1v8ti,twl4030-vusb1v87=regulator-vusb3v1ti,twl4030-vusb3v17=regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2ow@w@regulator-vsimti,twl4030-vsimow@-gpioti,twl4030-gpioG7=twl4030-usbti,twl4030-usb Sao}7=pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madcpower4ti,twl4030-power-idle-osc-offti,twl4030-power-idlei2c@48072000 ti,omap3-i2cxH 9txrxi2c2i2c@48060000 ti,omap3-i2cxH=txrxi2c3mailbox@48094000ti,omap3-mailboxmailboxxH @dsp  spi@48098000ti,omap2-mcspixH Amcspi1'@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH Bmcspi2' +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [mcspi3' tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0mcspi4'FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc15=>txrxBS default OXdnmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrxmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx^F defaultXdnwlcore@2 ti,wl1283x&mmu@480bd400ti,omap2-iommuxH mmu_isp7=mmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< commontxrxmcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx disabledmcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 commontxrxmcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR commontxrxmcbsp5txrx disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1timer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5timer@4903a000ti,omap3430-timerxI*timer6timer@4903c000ti,omap3430-timerxI+timer7timer@4903e000ti,omap3430-timerxI,timer8!timer@49040000ti,omap3430-timerxI-timer9!timer@48086000ti,omap3430-timerxH`.timer10!timer@48088000ti,omap3430-timerxH/timer11!timer@48304000ti,omap3430-timerxH0@_timer12.usbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hsohci@48064400ti,ohci-omap3xHD&Lehci@48064800 ti,ehci-omapxHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcxn>Jnand@0,0\micron,mt29f4g16abbda3w xkzbch8,,",(6 @/R@RQ(c{x-loader@0 x-loaderxbootloaders@80000u-bootxbootloaders_env@260000 u-boot-envx&kernel@280000kernelx(@filesystem@680000fsxhethernet@gpmcsmsc,lan9221smsc,lan9115*$  *$/<@6 $cQ*1K[iv default& xusb_otg_hs@480ab000ti,omap3-musbxH \]mcdma usb_otg_hs  usb2-phy2dss@48050000 ti,omap3-dssxH disabled dss_core|fckdispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H protophypll disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH  disabled dss_venc|fcktv_dac_clkssi-controller@48058000 ti,omap3-ssissiokxHHsysgddGgdd_mpu |q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portxHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portxHHtxrx&EFserial@49042000ti,omap3-uartxI PQRtxrxuart4lregulator-abb-mpu ti,abb-v1 `abb_mpu_ivaxH0rH0hbase-addressint-address| `sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singlexH%\7=pinmux_mmc3_core2_pinsE8:7=isp@480bc000 ti,omap3-ispxH H (Y/portsleds gpio-leds defaultuser0user0 R;noneled1led1 R;cpu0led2led2 R;nonewl12xx_vmmcregulator-fixed`vwl1271ow@w@ QVpgz7=regulator-vddvarioregulator-fixed `vddvario7=regulator-vdd33aregulator-fixed`vdd33a7=gpio_keys gpio-keys defaultsysboot2 sysboot2 Rsysboot5 sysboot5 Rgpio1gpio1 Rgpio2gpio2 R #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyti,bb-uvoltti,bb-uampti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplycd-gpiosvmmc-supplybus-widthcap-power-off-cardnon-removableref-clock-frequencytcxo-clock-frequency#iommu-cellsti,#tlb-entriesstatusreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,device-widthlabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespower#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typelinux,default-triggergpiostartup-delay-usenable-active-highvin-supplyregulator-always-onlinux,codegpio-key,wakeup