8(&mediatek,mt8135-evbp1mediatek,mt8135&!7MediaTek MT8135 evaluation boardchosenaliasesmemory=memoryI@cpu-mapcluster0core0Mcore1Mcluster1core0Mcore1McpusQmediatek,mt81xx-tz-smpcpu@0=cpuarm,cortex-a7I_ecpu@1=cpuarm,cortex-a7I_ecpu@100=cpuarm,cortex-a15I_ecpu@101=cpuarm,cortex-a15I_ereserved-memorymtrustzone-bootinfo@80002000mediatek,trustzone-bootinfoI clocks simple-busmdummy13m fixed-clockt]@_ e dummy32k fixed-clockt}_ e clk26m fixed-clockt_ e timerarm,armv7-timer&0   t]@soc simple-busmtopckgen@10000000mediatek,mt8135-topckgenIinfracfg@10001000 mediatek,mt8135-infracfgsysconI_ e pericfg@10003000mediatek,mt8135-pericfgsysconI0_ e pinctrl@10005000mediatek,mt8135-pinctrlI%$tuvsyscfg_pctl_a@10005000%mediatek,mt8135-pctl-a-syscfgsysconIP_etimer@10008000,mediatek,mt8135-timermediatek,mt6577-timerI q6 =system-clkrtc-clkpwrap@1000f000mediatek,mt8135-pwrap IpIpwrappwrap-bridge S  "Zpwrappwrap-bridge6  =spiwrapmt6397mediatek,mt6397mt6397regulatormediatek,mt6397-regulatorbuck_vpca15fvpca15u Pp0buck_vpca7fvpca7u Pp0buck_vsramca15 fvsramca15u Pp0buck_vsramca7 fvsramca7u Pp0buck_vcorefvcoreu Pp0buck_vgpufvgpuu `p0sbuck_vdrmfvdrmuO\0buck_vio18fvio18u 6`0ldo_vtcxofvtcxoldo_va28fva28ldo_vcamafvcamau`*ldo_vio28fvio28ldo_vusbfvusbldo_vmcfvmcuw@2Zldo_vmchfvmchu-2Zldo_vemc3v3 fvemc_3v3u-2Zldo_vgp1fvcamdu2Zldo_vgp2fvcamiouB@2Zldo_vgp3fvcamafuO2Zldo_vgp4fvgp4uO2Zldo_vgp5fvgp5uO-ldo_vgp6fvgp6uO2Zldo_vibrfvibru 2Zinterrupt-controller@10200030.mediatek,mt8135-sysirqmediatek,mt6577-sysirq%&I 0_eapmixedsys@10209000mediatek,mt8135-apmixedsysI syscfg_pctl_b@1020c000%mediatek,mt8135-pctl-b-syscfgsysconI _einterrupt-controller@10211000arm,cortex-a15-gic%&@I!! !@ !` _eserial@11006000*mediatek,mt8135-uartmediatek,mt6577-uartI` 36 *  =baudbus disabledserial@11007000*mediatek,mt8135-uartmediatek,mt6577-uartIp 46 +  =baudbus disabledserial@11008000*mediatek,mt8135-uartmediatek,mt6577-uartI 56 ,  =baudbus disabledserial@11009000*mediatek,mt8135-uartmediatek,mt6577-uartI 66 -  =baudbusokay #address-cells#size-cellscompatibleinterrupt-parentmodeldevice_typeregcpuenable-methodlinux,phandlerangesclock-frequency#clock-cellsinterruptsarm,cpu-registers-not-fw-configured#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsclocksclock-namesreg-namesresetsreset-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatus