us8nl(n4netxeon,r89rockchip,rk3288&chosenaliases7/i2c@ff650000Ui2c"M4defaultB  adisabledi2c@ff150000rockchip,rk3288-i2c ?Ui2c"O4defaultB! adisabledi2c@ff160000rockchip,rk3288-i2c @Ui2c"P4defaultB" adisabledi2c@ff170000rockchip,rk3288-i2c AUi2c"Q4defaultB#aokayserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7"MUUbaudclkapb_pclk4defaultB$aokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8"NVUbaudclkapb_pclk4defaultB%aokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9"OWUbaudclkapb_pclk4defaultB&aokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :"PXUbaudclkapb_pclk4defaultB'aokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;"QYUbaudclkapb_pclk4defaultB(aokaythermal-zonesreserve_thermal)cpu_thermal)tripscpu_alert0ppassive5*;*cpu_crit_ criticalcooling-mapsmap0* gpu_thermal)tripsgpu_alert0ppassive5+;+gpu_crit_ criticalcooling-mapsmap0+ tsadc@ff280000rockchip,rk3288-tsadc( %"HZUtsadcapb_pclk tsadc-apb4initdefaultsleepB,-,(>saokayUl5);)ethernet@ff290000rockchip,rk3288-gmac) macirq.8"fgc]MUstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethaok/rgmiiinput 0 'B@14defaultB2'00usb@ff500000 generic-ehciP "Uusbhost93>usbaokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T "UotgHhost94 >usb2-phyaokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X "UotgHotgPbq@@ 95 >usb2-phyaokayusb@ff5c0000 generic-ehci\ "Uusbhost adisabledi2c@ff650000rockchip,rk3288-i2ce <Ui2c"L4defaultB6aokaypmic@40silergy,syr827@VDD_CPU, Pp@+=75;pmic@41silergy,syr828AVDD_GPU, Pp@+=7rtc@51haoyu,hym8563Qxxin32k&84defaultB9pmic@5aactive-semi,act8846Z4defaultB:;HregulatorsREG1VCC_DDROOREG2VCC_IO2Z2Z5T;TREG3VDD_LOGB@B@REG4VCC_20REG5 VCCIO_SD2Z2Z5;REG6 VDD10_LCDB@B@REG7VCC_WL2Z2ZREG8VCCA_332Z2ZREG9VCC_LAN2Z2Z5/;/REG10VDD_10B@B@REG11VCC_18w@w@5;REG12 VCC18_LCDw@w@i2c@ff660000rockchip,rk3288-i2cf =Ui2c"N4defaultB< adisabledpwm@ff680000rockchip,rk3288-pwmh`4defaultB="^Upwmaokaypwm@ff680010rockchip,rk3288-pwmh`4defaultB>"^Upwm adisabledpwm@ff680020rockchip,rk3288-pwmh `4defaultB?"^Upwm adisabledpwm@ff680030rockchip,rk3288-pwmh0`4defaultB@"^Upwm adisabledbus_intmem@ff700000 mmio-sramp Cpsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfds5;power-controller!rockchip,rk3288-power-controllerk5D;Dpd_vio "chgfdehilkjpd_hevc "oppd_video "pd_gpu "syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv.Hjk$#gׄeрxhрxh5;syscon@ff770000rockchip,rk3288-grfsysconw5.;.watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt"p Oaokaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif Uhclkmclk"TAtx U4defaultBB. adisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UAAtxrxUi2s_hclki2s_clk"R4defaultBC adisabledvop@ff930000rockchip,rk3288-vop "Uaclk_vopdclk_vophclk_vopD def axiahbdclkEaokayport5 ; endpoint@0F5I;Iiommu@ff930300rockchip,iommu  vopb_mmuD aokay5E;Evop@ff940000rockchip,rk3288-vop "Uaclk_vopdclk_vophclk_vopD  axiahbdclkGaokayport5 ; endpoint@0H5J;Jiommu@ff940300rockchip,iommu  vopl_mmuD aokay5G;Ghdmi@ff980000rockchip,rk3288-dw-hdmi. g"hm UiahbisfrD aokayportsportendpoint@0I5F;Fendpoint@1J5H;Hinterrupt-controller@ffc01000 arm,gic-400  @ `   5;phyrockchip,rk3288-usb-phy.aokayusb-phy0  "]Uphyclk55;5usb-phy1 4"^Uphyclk53;3usb-phy2 H"_Uphyclk54;4pinctrlrockchip,rk3288-pinctrl.Cgpio0@ff750000rockchip,gpio-banku Q"@%58;8gpio1@ff780000rockchip,gpio-bankx R"A%gpio2@ff790000rockchip,gpio-banky S"B%gpio3@ff7a0000rockchip,gpio-bankz T"C%gpio4@ff7b0000rockchip,gpio-bank{ U"D%50;0gpio5@ff7c0000rockchip,gpio-bank| V"E%gpio6@ff7d0000rockchip,gpio-bank} W"F%gpio7@ff7e0000rockchip,gpio-bank~ X"G%5S;Sgpio8@ff7f0000rockchip,gpio-bank Y"H%hdmihdmi-ddc 1KKpcfg-pull-up?5L;Lpcfg-pull-downLpcfg-pull-none[5K;Kpcfg-pull-none-12ma[h 5M;Msleepglobal-pwroff1Kddrio-pwroff1Kddr0-retention1Lddr1-retention1Li2c0i2c0-xfer 1KK56;6i2c1i2c1-xfer 1KK5 ; i2c2i2c2-xfer 1 K K5<;<i2c3i2c3-xfer 1KK5!;!i2c4i2c4-xfer 1KK5";"i2c5i2c5-xfer 1KK5#;#i2s0i2s0-bus`1KKKKKK5C;Csdmmcsdmmc-clk1K5 ; sdmmc-cmd1L5 ; sdmcc-cd1L5;sdmmc-bus11Lsdmmc-bus4@1LLLL5;sdio0sdio0-bus11Lsdio0-bus4@1LLLLsdio0-cmd1Lsdio0-clk1Ksdio0-cd1Lsdio0-wp1Lsdio0-pwr1Lsdio0-bkpwr1Lsdio0-int1Lsdio1sdio1-bus11Lsdio1-bus4@1LLLLsdio1-cd1Lsdio1-wp1Lsdio1-bkpwr1Lsdio1-int1Lsdio1-cmd1Lsdio1-clk1Ksdio1-pwr1 Lemmcemmc-clk1Kemmc-cmd1Lemmc-pwr1 Lemmc-bus11Lemmc-bus4@1LLLLemmc-bus81LLLLLLLLspi0spi0-clk1 L5;spi0-cs01 L5;spi0-tx1L5;spi0-rx1L5;spi0-cs11Lspi1spi1-clk1 L5;spi1-cs01 L5;spi1-rx1L5;spi1-tx1L5;spi2spi2-cs11Lspi2-clk1L5;spi2-cs01L5;spi2-rx1L5;spi2-tx1 L5;uart0uart0-xfer 1LK5$;$uart0-cts1Luart0-rts1Kuart1uart1-xfer 1L K5%;%uart1-cts1 Luart1-rts1 Kuart2uart2-xfer 1LK5&;&uart3uart3-xfer 1LK5';'uart3-cts1 Luart3-rts1 Kuart4uart4-xfer 1 L K5(;(uart4-cts1Luart4-rts1Ktsadcotp-gpio1 K5,;,otp-out1 K5-;-pwm0pwm0-pin1K5=;=pwm1pwm1-pin1K5>;>pwm2pwm2-pin1K5?;?pwm3pwm3-pin1K5@;@gmacrgmii-pins1KKKKMMMMKKK MMKK52;2rmii-pins1KKKKKKKKKKspdifspdif-tx1 K5B;Bpcfg-output-highw5O;Opcfg-output-low5N;Nact8846pmic-vsel1N5:;:pwr-hold1O5;;;buttonspwrbtn1L5P;Ppmicpmic-int1L59;9usbhost-vbus-drv1K5Q;Qotg-vbus-drv1 K5R;Rexternal-gmac-clock fixed-clockhsY@ xext_gmac51;1gpio-keys gpio-keys4defaultBPbutton@0 8tGPIO Key Powerdvcc-host-regulatorregulator-fixed 84defaultBQ vcc_host+vcc-otg-regulatorregulator-fixed 8 4defaultBRvcc_otg+sdmmc-regulatorregulator-fixed sdmmc-supply2Z2Z S =T5;sys-regulatorregulator-fixed sys-supplyLK@LK@+57;7 #address-cells#size-cellscompatibleinterrupt-parenti2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supply#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmafcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplysystem-power-controller#pwm-cells#power-domain-cells#reset-cellsassigned-clock-rates#sound-dai-cellspower-domainsiommusremote-endpoint#iommu-cellsinterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowautorepeatgpioslinux,codelabellinux,input-typegpio-key,wakeupdebounce-intervalenable-active-highstartup-delay-us