v8o(&oh#radxa,rock2-squarerockchip,rk3288&7Radxa Rock 2 Squarechosen=serial2:115200n8aliasesI/i2c@ff650000N/i2c@ff140000S/i2c@ff660000X/i2c@ff150000]/i2c@ff160000b/i2c@ff170000g/dwmmc@ff0f0000m/dwmmc@ff0c0000s/dwmmc@ff0d0000y/dwmmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 &@4;GMcpu@501cpuarm,cortex-a12GMcpu@502cpuarm,cortex-a12GMcpu@503cpuarm,cortex-a12GMamba arm,amba-busUdma-controller@ff250000arm,pl330arm,primecell%@\4 gapb_pclkGMdma-controller@ff600000arm,pl330arm,primecell`@\4 gapb_pclk sdisableddma-controller@ffb20000arm,pl330arm,primecell@\4 gapb_pclkGEMEreserved-memoryUdma-unusable@fe000000oscillator fixed-clockzn6xin24mG M timerarm,armv7-timer0   zn6timer@ff810000rockchip,rk3288-timer  H 4 a gtimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 4Drvgbiuciuciu-driveciu-sample  @sokay1<FdefaultT ^jdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 4Eswgbiuciuciu-driveciu-sample ! @ sdisableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 4Ftxgbiuciuciu-driveciu-sample "@ sdisableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 4Guygbiuciuciu-driveciu-sample #@sokay1w<Fdefault T^saradc@ff100000rockchip,saradc $4I[gsaradcapb_pclk sdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi4ARgspiclkapb_pclk  txrx ,FdefaultT sdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi4BSgspiclkapb_pclk txrx -FdefaultT sdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi4CTgspiclkapb_pclktxrx .FdefaultT !"# sdisabledi2c@ff140000rockchip,rk3288-i2c >gi2c4MFdefaultT$ sdisabledi2c@ff150000rockchip,rk3288-i2c ?gi2c4OFdefaultT% sdisabledi2c@ff160000rockchip,rk3288-i2c @gi2c4PFdefaultT& sdisabledi2c@ff170000rockchip,rk3288-i2c Agi2c4QFdefaultT'sokayGMMMserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 74MUgbaudclkapb_pclkFdefaultT( sdisabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 84NVgbaudclkapb_pclkFdefaultT) sdisabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 94OWgbaudclkapb_pclkFdefaultT*sokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :4PXgbaudclkapb_pclkFdefaultT+ sdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;4QYgbaudclkapb_pclkFdefaultT, sdisabledthermal-zonesreserve_thermal-cpu_thermal-tripscpu_alert0ppassiveG.M.cpu_crit_ criticalcooling-mapsmap0. gpu_thermal-tripsgpu_alert0ppassiveG/M/gpu_crit_ criticalcooling-mapsmap0/ tsadc@ff280000rockchip,rk3288-tsadc( %4HZgtsadcapb_pclk 'tsadc-apbFinitdefaultsleepT031=0G]ssokaytG-M-ethernet@ff290000rockchip,rk3288-gmac) macirq284fgc]Mgstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 'stmmacethsok3inputrgmii4FdefaultT56  7 1'u0FO0usb@ff500000 generic-ehciP 4gusbhostX8]usbsokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 4gotgghostX9 ]usb2-phy sdisabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 4gotggotgo@@ X: ]usb2-phy sdisabledusb@ff5c0000 generic-ehci\ 4gusbhost sdisabledi2c@ff650000rockchip,rk3288-i2ce <gi2c4LFdefaultT;sokayact8846@5aactive-semi,act8846Z<=<<<<regulatorsREG1VCC_DDRO O8REG2VCC_IO2Z 2Z8GMREG3VDD_LOGB@ B@8REG4VCC_20 8G=M=REG5 VCCIO_SD2Z 2Z8GMREG6 VDD10_LCDB@ B@8REG7 VCCA_CODEC2Z 2Z8REG8VCCA_TP2Z 2Z8REG9 VCCIO_PMU2Z 2Z8G4M4REG10VDD_10B@ B@8REG11VCC_18w@ w@8REG12 VCC18_LCDw@ w@8syr827@40silergy,syr827@L8i{,vdd_cpu P p@<GMsyr828@41silergy,syr828AL8{, P pvdd_gpu@<hym8563@51haoyu,hym8563Qzxin32k&>FdefaultT?i2c@ff660000rockchip,rk3288-i2cf =gi2c4NFdefaultT@ sdisabledpwm@ff680000rockchip,rk3288-pwmhFdefaultTA4^gpwm sdisabledpwm@ff680010rockchip,rk3288-pwmhFdefaultTB4^gpwm sdisabledpwm@ff680020rockchip,rk3288-pwmh FdefaultTC4^gpwm sdisabledpwm@ff680030rockchip,rk3288-pwmh0FdefaultTD4^gpwm sdisabledbus_intmem@ff700000 mmio-sramp Upsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsGMpower-controller!rockchip,rk3288-power-controllerGHMHpd_vio 4chgfdehilkjpd_hevc 4oppd_video 4pd_gpu 4syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv2Hjk$#gׄeрxhрxhGMsyscon@ff770000rockchip,rk3288-grfsysconwG2M2watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt4p Osokaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif ghclkmclk4TEtx UFdefaultTF2sokayGVMVi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UEEtxrxgi2s_hclki2s_clk4RFdefaultTG sdisabledvop@ff930000rockchip,rk3288-vop 4gaclk_vopdclk_vophclk_vop H def 'axiahbdclkIsokayportG M endpoint@0JGNMNiommu@ff930300rockchip,iommu  vopb_mmu H .sokayGIMIvop@ff940000rockchip,rk3288-vop 4gaclk_vopdclk_vophclk_vop H  'axiahbdclkKsokayportG M endpoint@0LGOMOiommu@ff940300rockchip,iommu  vopl_mmu H .sokayGKMKhdmi@ff980000rockchip,rk3288-dw-hdmi2 g4hm giahbisfr H sokay;Mportsportendpoint@0NGJMJendpoint@1OGLMLinterrupt-controller@ffc01000 arm,gic-400G\  @ `   GMphyrockchip,rk3288-usb-phy2sokayusb-phy0m 4]gphyclkG:M:usb-phy1m44^gphyclkG8M8usb-phy2mH4_gphyclkG9M9pinctrlrockchip,rk3288-pinctrl2Ugpio0@ff750000rockchip,gpio-banku Q4@xG\G>M>gpio1@ff780000rockchip,gpio-bankx R4AxG\gpio2@ff790000rockchip,gpio-banky S4BxG\gpio3@ff7a0000rockchip,gpio-bankz T4CxG\GUMUgpio4@ff7b0000rockchip,gpio-bank{ U4DxG\G7M7gpio5@ff7c0000rockchip,gpio-bank| V4ExG\gpio6@ff7d0000rockchip,gpio-bank} W4FxG\gpio7@ff7e0000rockchip,gpio-bank~ X4GxG\GYMYgpio8@ff7f0000rockchip,gpio-bank Y4HxG\hdmihdmi-ddc PPpcfg-pull-upGQMQpcfg-pull-downpcfg-pull-noneGPMPpcfg-pull-none-12ma GRMRsleepglobal-pwroffPddrio-pwroffPddr0-retentionQddr1-retentionQi2c0i2c0-xfer PPG;M;i2c1i2c1-xfer PPG$M$i2c2i2c2-xfer  P PG@M@i2c3i2c3-xfer PPG%M%i2c4i2c4-xfer PPG&M&i2c5i2c5-xfer PPG'M'i2s0i2s0-bus`PPPPPPGGMGsdmmcsdmmc-clkPG M sdmmc-cmdQG M sdmcc-cdQGMsdmmc-bus1Qsdmmc-bus4@QQQQGMsdmmc-pwr PGZMZsdio0sdio0-bus1Qsdio0-bus4@QQQQsdio0-cmdQsdio0-clkPsdio0-cdQsdio0-wpQsdio0-pwrQsdio0-bkpwrQsdio0-intQsdio1sdio1-bus1Qsdio1-bus4@QQQQsdio1-cdQsdio1-wpQsdio1-bkpwrQsdio1-intQsdio1-cmdQsdio1-clkPsdio1-pwr Qemmcemmc-clkPGMemmc-cmdQGMemmc-pwr Qemmc-bus1Qemmc-bus4@QQQQemmc-bus8QQQQQQQQGMemmc-reset PGTMTspi0spi0-clk QGMspi0-cs0 QGMspi0-txQGMspi0-rxQGMspi0-cs1Qspi1spi1-clk QGMspi1-cs0 QGMspi1-rxQGMspi1-txQGMspi2spi2-cs1Qspi2-clkQG M spi2-cs0QG#M#spi2-rxQG"M"spi2-tx QG!M!uart0uart0-xfer QPG(M(uart0-ctsQuart0-rtsPuart1uart1-xfer Q PG)M)uart1-cts Quart1-rts Puart2uart2-xfer QPG*M*uart3uart3-xfer QPG+M+uart3-cts Quart3-rts Puart4uart4-xfer  Q PG,M,uart4-ctsQuart4-rtsPtsadcotp-gpio PG0M0otp-out PG1M1pwm0pwm0-pinPGAMApwm1pwm1-pinPGBMBpwm2pwm2-pinPGCMCpwm3pwm3-pinPGDMDgmacrgmii-pinsPPPPRRRRPPP RRPPG5M5rmii-pinsPPPPPPPPPPphy-rstSG6M6spdifspdif-tx PGFMFpcfg-output-highGSMSpmicpmic-intQG?M?usbhost-vbus-drvPGXMXemmc-pwrseqmmc-pwrseq-emmcTTFdefault U GMexternal-gmac-clock fixed-clockzsY@ ext_gmacG3M3vsys-regulatorregulator-fixedvcc_sysLK@ LK@8iG<M<soundsimple-audio-cardSPDIFsimple-audio-card,dai-link@1cpu Vcodec Wspdif-outlinux,spdif-ditGWMWvcc-host-regulatorregulator-fixed >FdefaultTX8 vcc_hostsdmmc-regulatorregulator-fixed Y FdefaultTZvcc_sd2Z 2ZGM #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathi2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removablemmc-pwrseq#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrx_delaytx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmainl1-supplyinl2-supplyinl3-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onfcs,suspend-voltage-selectorregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supply#pwm-cells#power-domain-cells#reset-cellsassigned-clock-rates#sound-dai-cellspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highreset-gpiossimple-audio-card,namesound-daienable-active-high