X8(t*socionext,ph1-ld6b-refsocionext,ph1-ld6b"&UniPhier PH1-LD6b Reference Boardchosen,serial0:115200n8aliases8/soc/serial@54006800@/soc/serial@54006900H/soc/serial@54006a00P/soc/i2c@58780000U/soc/i2c@58781000Z/soc/i2c@58782000_/soc/i2c@58783000d/soc/i2c@58784000i/soc/i2c@58785000n/soc/i2c@58786000memorysmemorycpussocionext,uniphier-smpcpu@0scpuarm,cortex-a9cpu@1scpuarm,cortex-a9cpu@2scpuarm,cortex-a9cpu@3scpuarm,cortex-a9clocksarm_timer_clk fixed-clock  uart_clk fixed-clockLi2c_clk fixed-clock  soc simple-busextbus simple-busBsupport_card simple-busethernet@00000000smsc,lan9118smsc,lan9115mii 4uart@000b0000 ns16550a l2-cache@500c0000 socionext,uniphier-system-cacheP P<Pl0)4Dserial@54006800socionext,uniphier-uartPokayTh@Wdefaulte !oserial@54006900socionext,uniphier-uartPokayTi@Wdefaulte #oserial@54006a00socionext,uniphier-uartPokayTj@Wdefaulte %oserial@54006b00socionext,uniphier-uart PdisabledTk@Wdefaulte oi2c@58780000socionext,uniphier-fi2cPokayXxWdefaulte )o eeprommicrochip,24lc128Pi2c@58781000socionext,uniphier-fi2c PdisabledXxWdefaulte  *o i2c@58782000socionext,uniphier-fi2c PdisabledXx Wdefaulte  +o i2c@58783000socionext,uniphier-fi2c PdisabledXx0Wdefaulte  ,o i2c@58784000socionext,uniphier-fi2cXx@ -o i2c@58785000socionext,uniphier-fi2cXxP o i2c@58786000socionext,uniphier-fi2cXx` o system-bus-controller@58c00000)socionext,uniphier-system-bus-controllerXY pinctrl@5f801000"socionext,ph1-ld6b-pinctrlsyscon_i2c0_grpvi2c0}i2c0i2c1_grpvi2c1}i2c1  i2c2_grpvi2c2}i2c2  i2c3_grpvi2c3}i2c3  uart0_grpvuart0}uart0uart1_grpvuart1}uart1uart2_grpvuart2}uart2uart3_grpvuart3}uart3usb0_grpvusb0}usb0usb1_grpvusb1}usb1usb2_grpvusb2}usb2usb3_grpvusb3}usb3timer@60000200arm,cortex-a9-global-timer`   o timer@60000600arm,cortex-a9-twd-timer`   o interrupt-controller@60001000arm,cortex-a9-gic`` #address-cells#size-cellscompatiblemodelstdout-pathserial0serial1serial2i2c0i2c1i2c2i2c3i2c4i2c5i2c6device_typeregenable-methodnext-level-cache#clock-cellsclock-frequencylinux,phandlerangesinterrupt-parentphy-modereg-io-widthinterruptsreg-shiftcache-unifiedcache-sizecache-setscache-line-sizecache-levelstatuspinctrl-namespinctrl-0clocksgroupsfunction#interrupt-cellsinterrupt-controller