Ð þí Ÿ8 ¬(ó tHiSilicon HI3519 DEMO Board!hisilicon,hi3519chosencpuscpu@0,cpu!arm,cortex-a78interrupt-controller@10300000!arm,cortex-a7-gic<M800 bclk_3m !fixed-clockjw-ÆÀbclock-reset-controller@12010000!hisilicon,hi3519-crgj‡8bsoc !simple-bus”¥serial@12100000!arm,pl011arm,primecell8 ¬·¾uartclkapb_pclkÊokayserial@12101000!arm,pl011arm,primecell8 ¬·¾uartclkapb_pclkÊdisableserial@12102000!arm,pl011arm,primecell8  ¬·¾uartclkapb_pclkÊdisableserial@12103000!arm,pl011arm,primecell80 ¬·¾uartclkapb_pclkÊdisableserial@12104000!arm,pl011arm,primecell8@ ¬·  ¾uartclkapb_pclkÊdisabletimer@12000000!arm,sp804arm,primecell¬@A8· ¾apb_pclkÊokaytimer@12001000!arm,sp804arm,primecell¬BC8· ¾apb_pclkÊdisabletimer@12002000!arm,sp804arm,primecell¬DE8 · ¾apb_pclkÊdisablespi@12120000!arm,pl022arm,primecell8 ¬ ·¾sspclkapb_pclkÑÊdisablespi@12121000!arm,pl022arm,primecell8 ¬ ·¾sspclkapb_pclkÑÊdisablespi@12122000!arm,pl022arm,primecell8  ¬ ·¾sspclkapb_pclkÑÊdisablesystem-controller@12020000 !hisilicon,hi3519-sysctrlsyscon8breboot!syscon-rebootØßæÞ­¾ïaliasesë/soc/serial@12100000memory@80000000,memory8€@ #address-cells#size-cellsmodelcompatibledevice_typereg#interrupt-cellsinterrupt-controllerphandle#clock-cellsclock-frequency#reset-cellsinterrupt-parentrangesinterruptsclocksclock-namesstatusnum-csregmapoffsetmaskserial0