Ð þí qHt(ý,€  ",Hisilicon HIP01 Development Board&2hisilicon,hip01-ca9x2hisilicon,hip01interrupt-controller@1e0010002arm,cortex-a9-gic=Ncgrefclk144mkhz 2fixed-clocko|•DŒhisi:refclk144khzgsoc  2simple-bus Ÿ amba-bus  2simple-busŸserial@100010002snps,dw-apb-uartc¦­baudclkapb_pclk¹ Ã Îokayserial@100020002snps,dw-apb-uartc ¦­baudclkapb_pclk¹ Ã! Îdisabledserial@100030002snps,dw-apb-uartc0¦­baudclkapb_pclk¹ Ã" Îdisabledserial@100060002snps,dw-apb-uartc`¦­baudclkapb_pclk¹ Ã Îdisabledsystem-controller@10000000*2hisilicon,hip01-sysctrlhisilicon,sysctrlcÕglobal_timer@a0002002arm,cortex-a9-global-timerc  Ã ¦local_timer@a0006002arm,cortex-a9-twd-timerc  Ã ¦cpus ãhisilicon,hip01-smpcpu@0ñcpu2arm,cortex-a9ccpu@1ñcpu2arm,cortex-a9cmemory@80000000ñmemoryc€€ interrupt-parent#address-cells#size-cellsmodelcompatible#interrupt-cellsinterrupt-controllerregphandle#clock-cellsclock-frequencyclock-output-namesrangesclocksclock-namesreg-shiftinterruptsstatusreboot-offsetenable-methoddevice_type