8{({P*mediatek,mt7623n-rfb-emmcmediatek,mt7623 ++7MediaTek MT7623N with eMMC reference boardopp-tableoperating-points-v2=Hopp-98000000P\Wopp-198000000P =Wopp-398000000PWopp-598000000P#Wopp-747500000P,Wopp-1040000000P=$W0opp-1196000000PGIWOopp-1300000000PM|mW cpus+emediatek,mt6589-smpcpu@0scpuarm,cortex-a7cpuintermediateM|mHcpu@1scpuarm,cortex-a7cpuintermediateM|mHcpu@2scpuarm,cortex-a7cpuintermediateM|mHcpu@3scpuarm,cortex-a7cpuintermediateM|mH pmuarm,cortex-a7-pmu0 dummy13m fixed-clock]@Hoscillator-1 fixed-clock}rtc32kHoscillator-0 fixed-clockclk26mH0thermal-zonescpu-thermal)7 tripscpu-passiveGިSzpassiveH cpu-activeGSzactiveH cpu-hotGSSzhotH cpu-critGS zcriticalcooling-mapsmap0^ 0c map1^ 0c map2^ 0c timerarm,armv7-timer 0   ]@rsyscon@100000009mediatek,mt7623-topckgenmediatek,mt2701-topckgensysconHsyscon@100010009mediatek,mt7623-infracfgmediatek,mt2701-infracfgsysconHsyscon@100030007mediatek,mt7623-pericfgmediatek,mt2701-pericfgsyscon0Hpinctrl@10005000mediatek,mt7623-pinctrl qrHcir-defaultHpins-cir .i2c0-defaultHpins-i2c0 KLi2c1-defaultpin-i2c1 9:i2c1-altHpin-i2c1 i2c2-defaultHpin-i2c2 MNi2c2-altpin-i2c2 z{i2s0-defaultHPpin-i2s0 1HIJ~ /i2s1-defaultpin-i2s1 !"#$% /keys-altHMpins-keys >leds-altpins-leds  mmc0defaultH%pins-cmd-dat$ opqrvwxyt>Kpins-clk u/pins-rst sKmmc0H&pins-cmd-dat$ opqrvwxyt> Kepins-clk u /epins-rst sKmmc1defaultH)pins-cmd-dat klmni> Kfpins-clk j/ pins-wp >Kpins-insert Kmmc1H*pins-cmd-dat klmni> Kfpins-clk j /fnanddefaultpins-ale t /fpins-dat$ oprvyxqsw> Kpins-we u Kfpcie_pin_defaultH/pins_cmd_dat pwm-defaultHpins-pwm spi0-defaultHpins-spi 5678spi1-defaultH"pins-spi  spi2-defaultH#pins-spi ehfguart0-defaultHpins-dat OPuart1-defaultHpins-dat QRuart2-defaultHpins-dat uart2-altpins-dat hdmi-defaultHGpins-hdmi {>/hdmi_ddc-defaultHJpins-hdmi-ddc |}syscfg@10005000%mediatek,mt7623-pctl-a-syscfgsysconPHpower-controller@100060005mediatek,mt7623-scpsysmediatek,mt2701-scpsyssysconX`lLQn mmmfgethifH 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Wclkokayxdefaultinterrupt-controller@10200100.mediatek,mt7623-sysirqmediatek,mt6577-sysirq  Hefuse@10206000,mediatek,mt7623-efusemediatek,mt8173-efuse `+calib@424$ Hsyscon@10209000=mediatek,mt7623-apmixedsysmediatek,mt2701-apmixedsyssyscon Hrng@1020f000mediatek,mt7623-rng  rnginterrupt-controller@10211000arm,cortex-a7-gic @!! !@ !` Hadc@11001000.mediatek,mt7623-auxadcmediatek,mt2701-auxadcmainHserial@11002000*mediatek,mt7623-uartmediatek,mt6577-uart  3- baudbusokayxdefaultserial@11003000*mediatek,mt7623-uartmediatek,mt6577-uart0 4. baudbusokayxdefaultserial@11004000*mediatek,mt7623-uartmediatek,mt6577-uart@ 5/ baudbusokayxdefaultserial@11005000*mediatek,mt7623-uartmediatek,mt6577-uartP 60 baudbus disabledpwm@11006000mediatek,mt7623-pwm`8S "topmainpwm1pwm2pwm3pwm4pwm5okayxdefaulti2c@11007000(mediatek,mt7623-i2cmediatek,mt6577-i2c pp ,  maindma+okayxdefaulti2c@11008000(mediatek,mt7623-i2cmediatek,mt6577-i2c p -  maindma+okayxdefaultwm8960@1a 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$!$$infra_sys_audio_clktop_audio_mux1_seltop_audio_mux2_seltop_audio_a1sys_hptop_audio_a2sys_hpi2s0_src_seli2s1_src_seli2s2_src_seli2s3_src_seli2s0_src_divi2s1_src_divi2s2_src_divi2s3_src_divi2s0_mclk_eni2s1_mclk_eni2s2_mclk_eni2s3_mclk_eni2so0_hop_cki2so1_hop_cki2so2_hop_cki2so3_hop_cki2si0_hop_cki2si1_hop_cki2si2_hop_cki2si3_hop_ckasrc0_out_ckasrc1_out_ckasrc2_out_ckasrc3_out_ckaudio_afe_pdaudio_afe_conn_pdaudio_a1sys_pdaudio_a2sys_pdaudio_mrgif_pd Nxy^@AuHNmmc@11230000(mediatek,mt7623-mmcmediatek,mt2701-mmc# 'T sourcehclkokayxdefaultstate_uhs%&'(mmc@11240000(mediatek,mt7623-mmcmediatek,mt2701-mmc$ ([ sourcehclkokayxdefaultstate_uhs)* ''syscon@160000007mediatek,mt7623-vdecsysmediatek,mt2701-vdecsyssysconH=syscon@1a0000005mediatek,mt7623-hifsysmediatek,mt2701-hifsyssysconH+pcie@1a140000mediatek,mt7623-pciespci@ 0@usubsysport0port1port2+` n+++ free_cksys_ck0sys_ck1sys_ck2+++pcie-rst0pcie-rst1pcie-rst2 ,-.%pcie-phy0pcie-phy1pcie-phy2% /okay89``xdefault/pcie@0,0+ 9okaypcie@1,0+ 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compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltenable-methoddevice_typeregclocksclock-namesoperating-points-v2#cooling-cellsclock-frequencyproc-supplyinterruptsinterrupt-affinity#clock-cellsclock-output-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicearm,cpu-registers-not-fw-configured#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxbias-disabledrive-strengthbias-pull-downinput-enablebias-pull-up#power-domain-cellsinfracfgreg-namesresetsreset-namesstatusregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-enable-ramp-delaymediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourcepinctrl-namespinctrl-0#io-channel-cells#pwm-cellsclock-div#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesreg-shiftreg-io-widthpower-domainsecc-engineinterrupt-namesassigned-clocksassigned-clock-parentsassigned-clock-ratespinctrl-1bus-widthmax-frequencycap-mmc-highspeedvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedcd-gpiosinterrupt-map-maskinterrupt-mapphysphy-namesbus-rangeranges#phy-cellsvusb33-supplyvbus-supply#dma-cellsmediatek,ethsysmediatek,pctlphy-modefull-duplexpausephy-handlereset-gpioscore-supplyio-supplylabelethernetrdma0rdma1serial0serial1serial2mediatek,smimediatek,larb-idmediatek,larbs#iommu-cellsmediatek,larbiommusremote-endpointmediatek,syscon-hdmicecmediatek,ibiasmediatek,ibias_upstdout-pathddc-i2c-buslinux,codemediatek,platformaudio-routingmediatek,audio-codec